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FEATURES
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| DESCRIPTION Trenton's SLI system host board (SHB) features a dual-core processor that provides two execution cores per SLI. The SLI’s Dual-Core Intel® Xeon® Processor LV 2.0GHz delivers superior processing capability and system performance using about half as much power as compared to previous generations of low voltage Intel Xeon processors. The processor is a 32-bit dual-core CPU that supports 36-bit memory addressing and Demand Based Switching. The SLI is a server-class PICMG® 1.3 SHB that supports one x4 and two x8 PCI Express links to a PICMG 1.3 backplane. An additional x4 PCIe link to a backplane is available using Trenton’s IOB31 expansion module. These links support PCI Express, PCI and PCI-X option cards on a PICMG 1.3 server-class backplane. |
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| PROCESSOR Dual-Core Intel® Xeon® Processor LV 1.66GHz to 2.0GHz* Processor Package: Micro-FCPGA (478-pin)  *Higher speeds as available
CHIPSET The SLI uses the Intel® E7520 chipset which operates on the 667Mz system bus and features a dual channel DDR2-400 memory interface. Three x8 PCI Express interfaces are supported by the SLI’s chipset. See the PCI Express Interfaces section for details on how the SLI implements PCI Express. The Intel® E6300ESB I/O Controller Hub supports the SLI’s dual Serial ATA/150 ports, four USB 2.0 interfaces, dual Ultra ATA/100 interfaces and the video and Ethernet controllers. The I/O Controller Hub’s LPC interface is routed to the board’s controlled impedance connector and supports an optional I/O expansion board (Trenton’s IOB30) for legacy I/O and serial port communications. The optional IOB31 expansion board supports legacy I/O via header connectors and provides an additional x4 PCI Express link to a PICMG 1.3 backplane. Communications between the Intel® E7520 Memory Controller Hub and the I/O Controller Hub occurs over a 266MB/s Hub Interface. DUAL ETHERNET INTERFACES - 10/100/1000BASE-T The SLI’s Gigabit Ethernet Controller (Intel® 82546EB) connects to the I/O Controller Hub via a PCI-X 64-bit/66MHz interface to provide high-speed 10/100/1000Base-T Ethernet interfaces on LAN ports 1 and 2. RJ-45 connectors, located on the I/O bracket, provide the physical interface to the Ethernet network. DUAL SERIAL ATA/150 PORTS The primary and secondary Serial ATA (SATA) ports on the SLI boards comply with the SATA 1.0 specification and support two independent SATA storage devices such as hard disks and CD-RW devices. SATA technology provides lower pin counts, reduced signaling voltages, simplified cabling, CRC error detection and hot-plug support. SATA produces higher performance interfacing by providing data transfer rates up to 150MB per second on each port. CACHE MEMORY (L2 AND L1) The Dual-Core Intel® Xeon® Processor LV 2.0GHz has a level two (L2) cache memory that is an integrated on-die Advanced Transfer Cache memory and is 8-way set associative with ECC to run at the full processor core frequency. The L2 cache memory size of 2MB is shared by the two processor cores. The Dual-Core Intel® Xeon® Processor LV 2.0GHz also features 32KB level one (L1) instruction and data caches. DDR2-400 MEMORY The four DIMM sockets on the SLI support a total memory capacity of 8GB and the DDR2 memory interface can operate as either a single-channel or dual-channel interface. The theoretical maximum memory bandwidth for single-channel operation is 3.2GB/s and 6.4GB/s for dual-channel mode. Each of the channels (A and B) terminates in two dual in-line memory module (DIMM) sockets. The System BIOS automatically detects memory type, size and speed. The memory modules used on the SLI must be PC2-3200 compliant. The SLI supports a DDR2-400 memory interface speed. Modules with a faster memory speed may be used; however, they will be automatically clocked down to the DDR2-400 memory interface speed by the System BIOS and the SHB’s memory interface components. DDR2-400 MEMORY DIMM SLOT POPULATION DDR2-400 memory modules are available as either single rank or dual rank DIMMs. A rank refers to the 72-bit unit of devices or DRAM chips that make up the PC2-3200 ECC registered 240-pin DDR2-400 DIMM. Single or dual rank memory modules must be placed in the SLIs DIMM sockets using prescribed population rules to ensure proper memory interface operation and performance. Installing two DIMMs which are identical in type, size and rank in DIMM sockets 1B and 1A results in dual-channel operation. If an additional pair of DIMMs is installed in sockets 2B and 2A, the DIMMs must be identical in type, size and rank to each other, but may be different in size from the pair installed in sockets 1B and 1A. If the modules in channel B and channel A (e.g., 1B and 1A) differ in size, the BIOS will use the size of the smallest DIMM. For more details refer to the SLI Memory Interface technical details. The following table explains the DDR2-400 DIMM population rules:
ULTRA XGA VIDEO INTERFACE The SLI is equipped with the third generation ATI® RAGE™ MOBILITY™ M1 video controller. The M1 enables 2D/3D video acceleration and provides 8MB of integrated video memory. In 2D mode the video controller supports pixel resolutions up to 1600 x 1200, and in 3D mode the maximum resolution provided is 1280 x 1024. The maximum color depth supported at these extremes is 16.7 million colors. Software drivers are available for popular operating systems. POWER REQUIREMENTS Typical Values - 100% Stressed via MS Windows HCT’s System Stress
Typical Values - System Idling In Windows XP Desktop
Tolerance for all voltages is +/- 5% and must be applied by the PICMG 1.3 backplane to edge connector C. TEMPERATURE/ENVIRONMENT
MECHANICAL PASSIVE COOLING The SLI has a board stack-up height of .76" (1.93cm) with the SHB's passive heat sink cooling solution. Airflow of at least 350LFM must always be present across the SHB's passive heat sink. The SLI's overall dimensions are 13.3" L (33.78cm) x 4.976" H (12.64cm) x .76" W (1.93cm). ACTIVE COOLING The SLI's optional active cooling solution has a cooling fan mounted on each CPU's passive heat sink resulting in a board stack-up height of 1.26" (3.20cm). Order the SLI with active cooling when 350LFM or more of airflow is not available for the processor. The chassis design must provide airflow of at least 100LFM across the SHB when using the active cooling solution. Note: The PICMG 1.3 board height specification is approximately .176" (4.47mm) taller than the PICMG 1.0 specification. However, relative PICMG 1.3 board height off the backplane is the same due to the shorter edge connectors of a PICMG 1.3 system host board and the shorter PCI Express connectors on a PICMG 1.3 backplane. |
PCI EXPRESS™ INTERFACES Trenton’s SLI system host board provides two x8 PCI Express links, one x4 PCI Express link and five PCI Express reference clocks routed to edge connectors A and B. These PCI Express links are used on SHB Express™ backplanes to support PCI Express option cards and bridge chips that provide PCI/PCI-X option card support. During system initialization the SLI automatically negotiates with the devices connected to the PCI Express links in order to set up communication between these devices. The net result is that the SLI system host board supports communication to x1, x4, x8, x16 PCI Express boards and PCI Express switch chips as well as PCI/PCI-X cards via PCI Express-to-PCI/PCI-X bridge technology on the backplane. PCI EXPRESS™ CONFIGURATION AND BUS SPEED
BIOS (FLASH) The SLI uses AMIBIOS8®. The flash BIOS resides in the 82802AC Firmware Hub (FWH). AMIBIOS8 contains features such as:
These optional boards provide legacy I/O connections via the Super I/O controller (LPC47B272). The I/O controller on an IOB30/31 connects to the SLI’s LPC Bus via the board’s controlled impedance connector. The following I/O interfaces are supported by the SLI via either the IOB30 or IOB31:
The operating systems that Trenton has tested that do not require the IOB30 or IOB31 are:
Microsoft® Windows® 2000 Microsoft® Windows® XP Microsoft® Windows® 2003 Server Microsoft® Windows® NT 4.0 RedHat Linux Fedora Core SUSE Linux Server Linux Enterprise Server QNX Neutrino Sun® Solaris™
IOB31 EXPANSION BOARD (OPTIONAL) The IOB31 supports all of the same I/O functions as the IOB30 using cable header connectors. There is no I/O plate on the IOB31. The IOB31 also provides a x4 PCI Express edge connector designed to fit into a PCI Express expansion slot on a PICMG 1.3 backplane. When used on the SLI system host board, the IOB31 provides an extra x4 PCI Express link to the backplane. BATTERY Built-in lithium battery for data retention of CMOS memory. QUAD USB INTERFACES The SLI supports four high-speed USB 2.0 ports for data transfers up to 480Mbit/sec. It also supports USB 1.1 devices for data transfers at 12 or 1.5Mbit/sec. Two USB 2.0 interface ports are located on the SLI’s I/O bracket. Two additional USB 2.0 headers are available on the SHB. The SLI supports the optional routing of two of the USB 2.0 interfaces to an SHB Express backplane. Contact Trenton if your application requires this feature. WATCHDOG TIMER The programmable watchdog timer is supported directly by the I/O Controller Hub. Two operating modes, free-running and one-shot, are available with this two-stage watchdog timer. Stage one can generate IRQ, SMI or SCI, and stage two generates a programable watchdog timer reset with a total range of 1ms to 10 minutes. AGENCY APPROVALS & INDUSTRY COMPLIANCE Designed for UL60950, CAN/CSA C22.2 No. 60950-00, EN55022:1998 Class B, EN61000-4-2:1995, EN61000-4-3:1997, EN61000-4-4:1995, EN61000-4-5:1995, EN61000-4-6:1996, EN61000-4-11:1994 STANDARDS - PCI Express Base Specification 1.0a - SHB Express™ System Host Board PCI Express specification - PCI Industrial Computer Manufacturers Group (PICMG®) 1.3 MEAN TIME BETWEEN FAILURES (MTBF) 227,929 POH (Power-On Hours) at 40 °C., per Bellcore | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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* Contact Trenton for the latest processor speed and availability. The stated bus speed, memory and communication interface speeds are component maximums; actual system performance may vary. |
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