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The setup of the configuration jumpers on the
SBC is described below. * indicates the default value of each jumper.
NOTE: For two-position jumpers (3-post), "LEFT" and "RIGHT" are defined with the bracket end of the board to the left, the edge connectors to the right.
If the processor core gets to a critical temperature, it slows itself down to half its normal speed. This jumper sets the way in which the LED displays in response to this self-limiting mode.
Install for real-time activity. The LED lights only when the processor is operating in slow-power mode. *
Remove for latched activity. The LED lights and stays on once the processor has gone into slow-power mode.
NOTE: Critical temperature is determined by the processor and cannot be altered by the user.
Install for one power-up cycle to reset the password to the default (null password).
Remove for normal operation. *
The Flash ROM has two programmable sections: the Boot Block for "flashing" in the BIOS and the Main Block for the executable BIOS and PnP parameters. Normally only the Main Block is updated when a new BIOS is flashed into the system.
|
JU10 |
JU11 |
All Blocks Write Enabled
Boot Block Write Protected
Block 2-16 Write Protected |
Remove *
Install
Remove |
Remove *
Remove
Install |
nstall on the LEFT to operate. *
Install on the RIGHT to clear.
NOTE: The CMOS Clear jumper works on power-up. To clear the CMOS, power down the system, install the jumper, then turn the power back on. Wait for at least two seconds and turn the power off. Then remove the jumper and turn the power on. When AMIBIOS displays the "CMOS Settings Wrong" message, press F1 to go into the BIOS Setup Utility, where you may reenter your desired BIOS settings, load optimal defaults or load failsafe defaults.
JU22 determines the voltage supplied to the device connected to connector P11A. The device may be a Compact Media Daughter Card (CMDC), a Hard Drive Adapter Kit (HDAK) or a conventional IDE drive. The CMDC supports either a CompactFlash T or Microdrive® storage device. The HDAK supports a laptop IDE hard drive.
nstall on the LEFT to supply +5 volts to the CMDC or HDAK. *
Install on the RIGHT to supply +3.3 volts to the CMDC.
Remove to use a conventional IDE drive.
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Install to inhibit IPMI functionality.
Remove to enable IPMI functionality. *
NOTE: On SBCs with revision J-03 and later, the JU23 2-pin header is not populated on non-IPMI versions of the processor board. On IPMI versions of the SBC with revision J-03 and later, the 2-pin header is populated but the jumper shunt must remain uninstalled.
On revisions of the CP16 prior to J-03, this 2-pin header was populated on both IPMI and non-IPMI SBCs; the default was Installed (IPMI functionality inhibited). If you have one of these earlier SBC models which has JU23 and does support IPMI, remove the jumper to enable IPMI functionality.
Configuration Jumpers (continued)
This jumper sets the maximum PCI-X speed for the on-board PCI/PCI-X Bus to the optional PMC card. Other speeds and modes for PMC are determined dynamically by the PMC card.
This jumper should remain at the factory setting of 133MHz, i.e., removed.
Remove for a maximum PCI-X speed of 133MHz. *
Install for a maximum PCI-X speed of 100MHz.
NOTE: The JU24 jumper is included on SBCs with revision J-03 and later.
These jumpers set the mode for the on-board CompactPCI Bus to the backplane.
The jumpers should remain at the factory setting as follows:
| JU30 | JU31 |
| PCI 66MHz | Install * | Right * |
NOTE: The JU30 and JU31 jumpers are included on SBCs with revision J-03 and later.
This jumper must be installed for the 400MHz Front Side Bus (FSB).
NOTE: The JU32 jumper is included on SBCs with revision J-03 and later.
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Each Ethernet interface has two LEDs for status
indication and an RJ-45 network connector.
| LED/Connector |
Description |
| Activity LED |
Green LED which indicates network activity.
This is the lower LED on the LAN connector (i.e., Toward the
edge connectors). |
| Off |
Indicates there is not a valid connection.
Transmit and receive are not possible. |
| On (solid) |
Indicates a link has successfully been established. |
| On (flashing) |
Indicates network transmit or receive activity. |
| Speed LED |
Yellow LED which identifies the connection
speed. This is the upper LED on the LAN connector (i.e., toward
the memory sockets). |
| Off |
Indicates a 10Mb/s connection. |
| On (solid) |
Indicates a 1000Mb/s connection. |
| On (flashing) |
Indicates a 100Mb/s connection. The LED
blinks Twice per second. |
|
| LED/Connector |
Description |
| RJ-45 Network |
The RJ-45 network connector requires a
category 5 (CAT5) unshielded twisted-pair (UTP) 2-pair cable
for a 100-Mb/s network connection or a category 3 (CAT3) or
higher UTP 2-pair cable for a 10-Mb/s network connection. A
category 5e (CAT5e) or higher UTP 2-pair cable is recommended
for a 1000-Mb/s (Gigabit) network connection. |
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Pin 1 on the connectors is indicated by the square
pad
on the PCB.
Dual RJ-45 connector, Amp/Tyco #1116353-4
Each individual RJ-45 connector is defined as follows:
| PIN |
SIGNAL |
| 1 |
TRP1+ |
| 2 |
TRP1- |
| 3 |
TRP2+ |
| 4 |
TRP3+ |
|
| PIN |
SIGNAL |
| 5 |
TRP3- |
| 6 |
TRP2- |
| 7 |
TRP4+ |
| 8 |
TRP4- |
|
3 pin single row header, Molex #22-23-2031
| PIN |
SIGNAL |
| 1 |
Gnd |
| 2 |
+12V |
| 3 |
FanTach |
|
4 pin single row header, Amp #640456-4
| PIN |
SIGNAL |
| 1 |
Speaker Data |
| 2 |
Key |
| 3 |
Gnd |
| 4 |
+5V |
|
9 position "D" right angle, Spectrum #56-402-001
| PIN |
SIGNAL |
| 1 |
Carrier Detect |
| 2 |
Receive Data-I |
| 3 |
Transmit Data-0 |
| 4 |
Data Terminal Ready-0 |
| 5 |
Signal Gnd |
|
| PIN |
SIGNAL |
| 6 |
Data Set Ready-I |
| 7 |
Request to Send-O |
| 8 |
Clear to Send-I |
| 9 |
Ring Indicator-I |
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40 pin dual row header, 3M #30340-6002HB
| PIN |
SIGNAL |
| 1 |
Reset |
| 3 |
Data 7 |
| 5 |
Data 6 |
| 7 |
Data 5 |
| 9 |
Data 4 |
| 11 |
Data 3 |
| 13 |
Data 2 |
| 15 |
Data 1 |
| 17 |
Data 0 |
| 19 |
Gnd |
| 21 |
DRQ 1 |
| 23 |
IOW |
| 25 |
IOR |
| 27 |
IORDY |
| 29 |
DACK 1 |
| 31 |
IRQ15 |
| 33 |
Add 1 |
| 35 |
Add 0 |
| 37 |
CS 1S |
| 39 |
IDEACTS |
|
| PIN |
SIGNAL |
| 2 |
Gnd |
| 4 |
Data 8 |
| 6 |
Data 9 |
| 8 |
Data 10 |
| 10 |
Data 11 |
| 12 |
Data 12 |
| 14 |
Data 13 |
| 16 |
Data 14 |
| 18 |
Data 15 |
| 20 |
NC |
| 22 |
Gnd |
| 24 |
Gnd |
| 26 |
Gnd |
| 28 |
SELPDS |
| 30 |
Gnd |
| 32 |
NC |
| 34 |
SCBL DET * |
| 36 |
Add 2 |
| 38 |
CS 3S |
| 40 |
Gnd |
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* For ATA/66 and ATA/100 drives, which should be set for Cable Select
for proper speed operation. If other drives are detected, pin definition
is Gnd.
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15 pin HD15 connector, Amp #1-1470250-3
| PIN |
SIGNAL |
| 1 |
Red |
| 2 |
Green |
| 3 |
Blue |
| 4 |
NC |
| 5 |
Gnd |
|
| PIN |
SIGNAL |
| 6 |
Gnd |
| 7 |
Gnd |
| 8 |
Gnd |
| 9 |
+5V |
| 10 |
Gnd |
|
| PIN |
SIGNAL |
| 11 |
NC |
| 12 |
EEDI |
| 13 |
HSYNC |
| 14 |
VSYNC |
| 15 |
EECS |
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4 USB vertical connector, Molex #67-329-0000
(+5V fused with self-resetting fuse)
| PIN |
SIGNAL |
| 1 |
+5V - USB1 |
| 2 |
USB1- |
| 3 |
USB1+ |
| 4 |
Gnd - USB1 |
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4 USB vertical connector, Molex #67-329-0000
(+5V fused with self-resetting fuse)
| PIN |
SIGNAL |
| 1 |
+5V - USB0 |
| 2 |
USB0- |
| 3 |
USB0+ |
| 4 |
Gnd - USB0 |
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4 pin single row header, Amp #640456-4
| PIN |
SIGNAL |
| 1 |
Gnd |
| 2 |
GPO (General Purpose Output) |
| 3 |
CI (Chassis Intrusion Input) |
| 4 |
OVT (Over Temperature) |
3 pin single row header, Molex #22-23-2031
| PIN |
SIGNAL |
| 1 |
Gnd |
| 2 |
+12V |
| 3 |
FanTach |
|
2 pin single row header, Amp #640456-2
| PIN |
SIGNAL |
| 1 |
SMB Clock |
| 2 |
SMB Data |
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The
Double Data Rate (DDR) memory interface consists of a single channel
which terminates in a dual in-line memory module (DIMM) socket and
supports auto detection of up to 2GB of memory. The System BIOS
automatically detects memory type, size and speed.
The SBC uses industry standard 72-bit wide gold
finger PC1600 or PC2100 memory modules in a 184-pin DIMM socket.
Modules may
be either PC1600 or PC2100; sizes can range from 128MB to 2GB. Because
the memory interface consists of a single channel, the SBC has a
maximum memory bandwidth of 1600MB/s. All memory modules must have
gold contacts.
The SBC supports DIMMs which are PC1600/PC2100
compliant and have the following features:
- 184-pin with gold-plated contacts
- ECC (72-bit) DDR memory
- Registered configuration
- X4, x8 construction
- Non-stacked (NS)
Trenton recommends
using non-stacked DIMM modules in order to avoid potential
physical interference on the SBC which may occur when using stacked
memory.
| DIMM Size |
DIMM Type |
ECC |
Component
Construction |
| 128 MB |
Registered |
16M x 72 |
x4, x8, NS |
| 256 MB |
Registered |
32M x 72 |
x4, x8, NS |
| 512 MB |
Registered |
64M x 72 |
x4, x8, NS |
| 1 GB |
Registered |
128M x 72 |
x4, x8, NS |
| 2 GB |
Registered |
256M x 72 |
x4, x8, NS |
* Intel and Pentium are registered trademarks
of Intel Corporation.
All other product names are trademarks of
their respective owners. |
CP10
Product Detail.
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